MICROCHIP AC480 Fpga Sfp Module PolarFire

Мушаххасоти:

• Номи маҳсулот: AC480 Application Note PolarFire FPGA SFP+ Module
• Истеҳсолкунанда: Микросемия
• Идораи марказӣ: Як корхона, Алисо Виежо, CA 92656 ИМА
• Тамос:
  • Дар дохили ИМА: +1 800-713-4113
  • Берун аз ИМА: +1 949-380-6100
  • Фурӯш: +1 949-380-6136
  • Факс: +1 949-215-4996
  • Почтаи электронӣ: sales.support@microsemi.com
  • Webсайт: www.microsemi.com

Дастурҳои истифодаи маҳсулот

PolarFire FPGA SFP+ Module
The PolarFire FPGA SFP+ Module is designed to provide high-speed data communication capabilities.

Block Diagram of the SFP+ Module
The block diagram illustrates the internal components and connections of the SFP+ module.

SFP+ Module Dimensions
Refer to the provided dimensions for proper fitting and integration of the SFP+ module.

Таърихи ревизия
Таърихи таҷдиди назар тағйиротҳоеро, ки дар ҳуҷҷат амалӣ карда шудаанд, тавсиф мекунад. Тағйирот аз рӯи навор аз нашри охирин сар карда номбар карда мешаванд.

Баррасии 1.0
Нашри аввалини ин ҳуҷҷат.

PolarFire FPGA SFP+ Module

Microsemi’s 10G optical SFP+ module is a system-level optical transceiver solution built with the lowest power, smallest form factor, and highly secure PolarFire® FPGA.

PolarFire FPGAs provide the following features required for the data communication applications:

• Small form factor with a 11 mm x 14.5 mm
• Mid-range device variant (MPF200 FPGA) containing 192K LEs (DFFs + LUTs)
• Low-power advantages required for SFP/SFP+ based applications
• Highly secure and reliable with in-line encryption
• High-performance transceivers at 12.7G

Thus, PolarFire FPGA-based smart SFP/SFP+ applications saves design time and cost without compromising performance. SFP+ applications around Routers, OAM, OLT/ONU, OTN, 1588, SyncE, and SDN can be built using PolarFire FPGAs.

For more information about the PolarFire FPGA family, see PolarFire FPGAs.
The MPF200T-FCSG325 device is used in the SFP+ module. MPF200 includes 192K LEs (DFFs + LUTs) and comes with a 11 mm × 14.5 mm form factor, which makes this device package the best fit for SFP+ applications.

This application note describes how the PolarFire FPGA can be used in building an SFP+ module and provides guidelines to:

• Build an FPGA based SFP+ module within the given small form factor.
• Design an efficient power integrity for the module and to design a high-performance signal integrity for the high-speed traces.

Block Diagram of the SFP+ Module

The following figure shows the block diagram of the SFP+ module.

The SFP+ module contains the following components and provisions:

• PolarFire MPF200T-FCSG325 FPGA
• PolarFire FPGA auxiliary circuit for power-up
• Clocking and programing circuit
• Line drivers
• Маҳдуд кардан ampосебдидагон
• Муоширати оптикӣ:
  • Receiver Optical sub-assembly (ROSA) required for optical communication
  • Transmitter optical sub-assembly (TOSA) required for optical communication
• Provision for one high-speed serial TX/RX going form PolarFire FPGA to Line driver/ampзиндатар
• A few side-band signals to control other circuit
• Пайвасткунаки канори

SFP+ Module Dimensions
The module outline dimensions are shown in the following figure.

Шарҳ: All dimensions in the figure are in mm.

For more information about the SFP+ from factor, see the SFF-8432 specification.

Hardware Reference Design Details

FPGA Block Diagram
The following hardware block diagram shows the typical architecture of an FPGA based SFP+ module.

Power Regulation and Consumption
The PolarFire FPGA requires core current (VDD) and transceiver current (VDDA) at 1V0. Other Voltage rails VDD25 and VDDA25 at 2V5, and VDD18 at 1V8 are shown in Figure 4, page 6. The core current (VDD) depends on the size of the design programmed on the FPGA.

For a typical SFP+ application, the core current lies between 1A to 2A. It is highly recommended to check the power consumption (using Microsemi Power Estimator) for different rails before finalizing the power numbers because it may vary with the design. The Power Estimator tool is available at https://www.microsemi.com/document-portal/doc_download/136554-polarfire-power-estimator.

The following table lists the recommended decoupling capacitors to be used for the PolarFire device.

Ҷадвали 1 • Recommended De-coupling Capacitors

Transceiver Scheme
The following figure shows how the transceiver connects to the edge connector, Laser driver, and the ampгардиши умр.

As shown in Figure 5, page 6, the edge connector interfaces with Lane 2 of the PolarFire XCVR block,and the Laser Driver and amplifier unit interfaces with Lane 0.
For more information about the PolarFire Transceiver, see UG0677: PolarFire FPGA Transceiver User Guide.

Transceiver Reference Clock
A 156.25 MHz oscillator is available on the module to provide reference clock to the PolarFire transceiver block at the XCVR_0A_REFCLK pin. The oscillator output is standard LVDS. For more information about the electrical characteristics and supporting standards of the reference clock, see DS0141: PolarFire FPGA Datasheet.

FPGA Programming Interfaces
PolarFire FPGA can be programmed through SPI. Test points are available for JTAG signals only for debug purpose. The following section describes the SPI programming interface.

1. SPI Programming
   In the SPI programming scheme, the PolarFire FPGA on the SFP+ module programs itself from the SPI
   Flash. SPI supports in-application programming (IAP) and auto-update. The following figure shows the SPI programming scheme.

To enable IAP programming, the following FPGA pins must be set high:

• A10 (SC_SPI_ENABLE)
• A9 (SC_IO_CFG_INTERFACE)

The SPI Flash specifications on the module are as follows:

• Density: 128 Mb
• Ҷилдиtage: 2.7 V to 3.6 V (S25FL127SABNFI101)
• Дастгирии режими SPI: Усулҳои 0 ва 3
• Dedicated BANK: 3
  For more information on FPGA programming, see UG0714: PolarFire FPGA Programming User Guide.

Laser Driver and Limiting Ampзиндатар
The module contains a combination of VCSEL driver and limiting amplifier with a 3-wire digital control interfaced from FPGA. This 3-wire interface enables the FPGA to access the registers of the Laser driver and ampлифер.

Ҷойгиркунии ҷузъҳо
This section describes the top and side view of the FPGA placement.

1. Top Side FPGA Placement
   The following figure shows the top view of the FPGA placement.

Bottom Side FPGA Placement
Figure 10, page 9 shows the bottom view of the FPGA placement.

Тарҳбандии модул

1. Stack Up and Material
   The PolarFire SFP+ module is designed with six-layer PCB and Material used is Nelco 4000-13SI.
   The stack-up is as follows:
   1. боло
   2. GND1
   3. SIG1
   4. Қувва
   5. GND2
   6. Поён
      Шарҳ: The total PCB thickness is 1 mm with an accuracy of +/- 0.1 mm.
2. Break-Out Layer By Layer
   The Layer-by-Layer break-out is shown in the figures:
   1.  Қабати боло
      The following figure shows the top layer.
   2. GND1 Layer
      The following figure shows the GND1 layer.
   3. SIG1 Layer
      The following figure shows the SIG1 layer.
   4. Power Layer
      Figure 14, page 11 shows the power layer.
   5. GND2 Layer
      The following figure shows the GND2 Layer.
   6. Қабати поён
      The following figure shows the bottom layer.

Power Integrity Recommendations
The recommended board capacitors are listed in Table 1,for SFP+ application. The bulk capacitors for VDD mentioned in Table 1,are for the PolarFire device only. Table 1, does not list the capacitors required for the output of the regulator. The regulator output must follow the capacitor specifications of the regulator vendor.

• The bulk capacitor recommendations for VDD are based on 1.5A of consumption.
• Care must be taken while routing the VDD plane. Ensure that the plane is routed as a dedicated plane so that no IR drop occurs at any location of the net. This would also ensure the ripple for VDD is at a minimum.
• Place all 0.1 μF and 0.01 μF capacitors under device BGA.
  Шарҳ: For information about the recommended connections for unused power supplies, see Figure 3 and 4 of UG0726: PolarFire FPGA Board Design User Guide.

Signal Integrity Recommendations
The following guidelines are recommended for high speed transceiver trace routing:

1. Match length between P and N within 1 mil.
2. Maintain the impedance between 85 to 100 ohms.
3. Model via, BGA pad and connector discontinuities to match the trace impedance.
4. Use loosely coupled differential traces.
5. Use low loss PCB materials.
6. Use low roughness copper PCB material.
   For more information about the routing of high-speed signals, see section 4.2 of UG0726: PolarFire FPGA Board Design User Guide.

IBIS-AMI Simulation
IBIS-AMI simulation was performed on one of the traces going from PolarFire FPGA TX to SFP male connector. And, the eye diagram was captured at the connector. The simulation topology is shown in Figure 18, page 13.

Шарҳ: The IBIS-AMI models are available at: https://www.microsemi.com/products/fpga-soc/design-resources/ibis-models/ibis-models-polarfire

• The simulations parameters for IBIS-AMI are as follows:
  • TX ampшиддат: 400 мВ
  • Бекор кардани таъкид: 0 дБ
  • Driver impedance: 100 ohms
• As shown in Figure 18, page 13, the eye diagram included the SFP compliant eye mask. The eye diagram passes the SFP eye mask specification in the simulation. The eye diagram indicates that the trace is optimized for all discontinuities.

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